CMOS TFT Op-Amps: Performance and Limitations

Author

Dey, Aritra ; Avendanno, Adrian ; Venugopal, Sameer ; Allee, David R. ; Quevedo, Manuel ; Gnade, Bruce

Author_Institution

Sch. of Electr., Comput., & Energy Eng., Arizona State Univ., Tempe, AZ, USA

Volume

32

Issue

5

fYear

2011

fDate

5/1/2011 12:00:00 AM

Firstpage

650

Lastpage

652

Abstract

In this letter, we demonstrate the feasibility of building thin-film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) operational amplifiers (op-amps) at low temperature (180°C) for large-area sensor applications. The classic two-stage Miller-compensated CMOS design is built using a-Si:H and pentacene TFTs. In addition, we have studied the impact of electrical stress-induced aging of TFTs on op-amp performance using two different kinds of biasing circuits.

Keywords

CMOS analogue integrated circuits; operational amplifiers; silicon; thin film transistors; CMOS; CMOS TFT op-amps; Si; TFT; biasing circuits; complementary metal-oxide-semiconductor; electrical stress-induced aging; large-area sensor applications; operational amplifiers; temperature 180 degC; thin-film transistor; two-stage Miller-compensated CMOS design; Amorphous silicon; CMOS integrated circuits; Degradation; Logic gates; Pentacene; Topology; Transistors; $V_{T}$; Analog-to-digital converter (ADC); hydrogenated amorphous silicon (a-Si:H); op-amp; pentacene; thin-film transistors (TFTs); unity-gain frequency (UGF);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2121891

Filename

5750018