Modelling output waveform and propagation delay of a CMOS inverter in the submicron range

An accurate, analytical model is presented for the evaluation of the CMOS inverter delay in the submicron regime. Following an exhaustive analysis of the inverter operation, accurate expressions of the output response to an input ramp are derived, which result in the analytical calculation of the propagation delay. These expressions are valid for all the inverter operation regions and input waveform slopes, and take into account the influences of the short-circuit current and the gate-drain coupling capacitance. The effective output transition time of the inverter is determined, in order to map the real output waveform to a ramp waveform for the model to be applicable to CMOS gate chains. The results are in very good agreement with SPICE simulations