Title :
A novel critical path heuristic for fast fault grading
Author :
Favalli, M. ; Olivo, P. ; Ricco, B.
Author_Institution :
DEIS, Bologna Univ., Italy
fDate :
4/1/1991 12:00:00 AM
Abstract :
A novel fault grading heuristic is presented, based on the critical path tracing technique that tackles the problems associated with fan-out reconverging nodes (FORNs) without using forward propagation of the fault effects. To determine the criticality status of a fan-out reconverging node, which can differ from that of its fan-out branches (FOBs), the concepts of evidencing and masking paths are used. Using the statistics from exact fault simulations, heuristic rules are derived for the generation of masking and evidencing paths. The results obtained on benchmark circuits show good accuracy for fault coverage estimates and a computation time linear in the number of gates and comparable to that of the fault-free simulation
Keywords :
fault location; logic testing; critical path heuristic; critical path tracing technique; evidencing; exact fault simulations; fan-out reconverging nodes; fast fault grading; fault coverage estimates; heuristic rules; masking paths; Circuit faults; Circuit simulation; Circuit testing; Complexity theory; Computational modeling; Data structures; Electrical fault detection; Fault detection; Statistics; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
