A method of reducing aliasing in a built-in self-test environment

Author

Akiyama, Keiho ; Saluja, Kewal K.

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

Volume

10

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

548

Lastpage

553

Abstract

A method of reducing aliasing in built-in self-test of VLSI circuits is proposed. The method is based on the use of transition count testing. A new formulation of the problem is given in terms of finding a test generator as opposed to solving the problem at the data compaction end. An algorithm is proposed which can be used to find a counter-based test pattern generator. This test generator tests a circuit exhaustively or pseudo-exhaustively so that the aliasing is reduced substantially provided the data compactor used is a transition counter. Experimental results are presented to substantiate these claims

Keywords

VLSI; automatic testing; built-in self test; integrated circuit testing; BIST environment; VLSI circuits; aliasing reduction; built-in self-test; counter-based test pattern generator; data compactor; transition count testing; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Compaction; Computational modeling; Test pattern generators; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.75640

Filename

75640