GF(2m) multiplication over triangular basis for design of Reed-Solomon codes

Bit-serial and bit-parallel multiplication architectures for GF(2m) are presented, using a triangular basis representation of field elements. The paper is a development of the work originally presented by Hasan and Bhargava. It is shown that, by forcing these multipliers to operate entirely over the triangular basis, lower latency delays and hardware savings can be made. Also, a more flexible definition of the triangular basis is presented, which allows a number of triangular bases to any given basis to be defined. It is shown that when the defining irreducible polynomial is a trinomial, the triangular basis is a simple permutation of the polynomial basis elements. Furthermore, if the defining irreducible polynomial is a pentanomial of a certain form the triangular basis to polynomial basis conversion requires minimal hardware and a reordering of basis coefficients