VHDL as input for high-level synthesis

High-level synthesis is defined, and the feasibility of high-level synthesis from a behavioral, sequential description in VHDL (VHSIC hardware description language) is examined. It is seen that in some cases the semantics and descriptive power of the language create difficulties for high-level synthesis, and in other cases the high-level synthesis framework used imposes limitations. Restrictions in the form of rules are suggested for overcoming these difficulties. It is shown that although VHDL semantics were initially defined in terms of simulation, they do not pose any fundamental problems for high-level synthesis.<>