Abstract :
An automatic design-for-testability (DFT) rule checker that can be used during early design stages at the register-transfer level is described. The system uses expert-system technology to check the correspondence of a rule set to a register-transfer level description of the design. In addition, it runs quickly and interactively, supports hierarchical design by checking subcircuits and groups of subcircuits, and provides concrete references about possible rule violations in the circuit and advice on how to eliminate them. The system accepts arbitrary DFT rule sets as input and analyzes highly integrated circuits hierarchically. Its output provides the location of rule violations or, if there are no violations, DFT descriptions of the circuit and the analysis protocol.<>
Keywords :
automatic testing; expert systems; logic CAD; analysis protocol; automatic testing; expert-system technology; hierarchical design; highly integrated circuits; register-transfer level; rule violations; rule-based design-for-testability rule checker; Automatic control; Automatic testing; Circuit synthesis; Circuit testing; Clocks; Design for testability; Logic testing; Production; Sequential analysis; System testing;
