Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

Author

Wu, Qingqing ; Chen, Jing ; Lu, Zhichao ; Zhou, Zhenming ; Luo, Jiexin ; Chai, Zhan ; Yu, Tao ; Qiu, Chao ; Li, Le ; Pang, Albert ; Wang, Xi ; Fossum, Jerry G.

Author_Institution

State Key Lab. of Functional Mater. for Inf., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China

Volume

33

Issue

6

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

743

Lastpage

745

Abstract

A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case retention time as well as the fast write speed. The operation power dissipation is dramatically reduced while maintaining high sense margin. In addition, FBGC demonstrates excellent endurance performance and nondestructive read operation.

Keywords

CMOS integrated circuits; DRAM chips; embedded systems; silicon-on-insulator; embedded memories; gate drain underlap; gate source overlap; high performance floating body gate DRAM cell; nondestructive read operation; partially depleted SOI CMOS technology; power dissipation; retention time; silicon-on-insulator; write speed; CMOS technology; Current measurement; Logic gates; Random access memory; Reliability; Transistors; Capacitorless DRAM; SOI floating-body cell (FBC); overlap; tunneling field-effect transistor (T-FET); underlap;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2012.2190031

Filename

6184278