Title :
An appropriate device figure of merit for bipolar CML
Author :
Greeneich, Edwin W.
Author_Institution :
Center for Solid State Electron. Res., Arizona State Univ., Tempe, AZ, USA
Abstract :
The effects of base resistance, base transit time, and junction capacitances play a key role in the propagation delay of high-speed bipolar logic gates. A simple device figure of merit for transistors used in current mode logic (CML) circuits, based on minimum propagation delay, is developed. This delay is derived from the large-signal 3-dB cutoff frequency of the CML gate. Results are shown to be applicable for a wide range of device and circuit parameters.<>
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; optimisation; semiconductor device models; CML gate; ECL gates; base resistance; base transit time; current mode logic; device figure of merit; figure of merit for transistors; gate delay; high-speed bipolar logic gates; junction capacitances; large-signal 3-dB cutoff frequency; minimum propagation delay; models; propagation delay; Bipolar transistors; Capacitance; Capacitors; Cutoff frequency; Delay effects; Logic circuits; Logic devices; Logic gates; Magneto electrical resistivity imaging technique; Propagation delay;
Journal_Title :
Electron Device Letters, IEEE
