Title :
PMOS input merged bipolar/sidewall MOS transistors (PBiMOS transistors)
Author :
O, Kenneth ; Reif, Rafael ; Lee, Hae-Seung
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
A concept of merging vertical n-p-n bipolar and sidewall PMOS transistors into merged PBiMOS transistors is described. This concept allows device structures which perform more complex functions to be integrated into a given area. The feasibility of this concept is demonstrated by fabricating and DC characterizing PBiMOS transistor structures which occupy approximately 1.1 times the area of a single n-p-n bipolar transistor. The PMOS sidewall transistor characterization results suggest that a reasonable control of the key device parameters may be achieved. These results also suggest that, for the 23-nm gate oxide thickness, the doping requirements for the n/sup -/ collector of the n-p-n bipolar and the channel of the sidewall PMOS transistors are similar.<>
Keywords :
bipolar transistors; insulated gate field effect transistors; integrated circuit technology; 23 nm; DC characterizing; MOSFET bipolar transistors merging; PBiMOS transistors; PMOS input merged bipolar/sidewall MOS transistors; area; complex functions; control of key device parameters; device structures; doping requirements; feasibility; gate oxide thickness; merged PBiMOS transistors; merged device structures; sidewall PMOS transistors; vertical n-p-n bipolar; BiCMOS integrated circuits; Bipolar transistor circuits; Bipolar transistors; Doping; Fabrication; Logic circuits; Logic devices; Logic gates; MOSFETs; Merging;
Journal_Title :
Electron Device Letters, IEEE
