Title :
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation
Author :
Lee, Won-Young ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Abstract :
This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13-μm CMOS technology. The rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with output drivers and an embedded 2:1 MUX at 5.4-Gb/s data rate.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; clocks; integrated circuit testing; jitter; phase detectors; phase noise; CDR circuit; CMOS technology; clock; data recovery circuit; half-rate linear phase detector; minimal phase noise degradation; operation mode; output driver; output phase noise degradation problem; phase error; power 138 mW; power dissipation; rms jitter; seamless loop transition scheme; size 0.13 mum; stability problem; Clocks; Detectors; Frequency locked loops; Phase noise; Tracking loops; Voltage-controlled oscillators; Dual-loop architecture; clock and data recovery (CDR); phase noise;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2012.2190678
