Leakage mechanisms in the heavily doped gated diode structures

Author

Hi Han, Chul ; Kim, Kwan

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

Volume

12

Issue

2

fYear

1991

Firstpage

74

Lastpage

76

Abstract

A leakage current model is presented which shows very good agreement with reported experimental results on gated diode structures with contemporary ULSI dimensions. The leakage current is modeled as the Shockley-Read-Hall generation current, enhanced by the Poole-Frenkel effect and trap-assisted tunneling. The model shows very good agreement on gate voltage, temperature, and oxide thickness dependence for the normal operating voltage range. It is found from the model that the doping range from 2*10/sup 18/ to 1*10/sup 19/ cm/sup -3/ gives the most significant degradation to the leakage characteristics in trench-type DRAM cells and the drain of MOSFETs.<>

Keywords

DRAM chips; MOS integrated circuits; VLSI; integrated memory circuits; leakage currents; semiconductor device models; semiconductor diodes; Poole-Frenkel effect; Shockley-Read-Hall generation current; ULSI dimensions; degradation; doping range; drain of MOSFETs; experimental results; gate voltage dependence; heavily doped gated diode structures; leakage characteristics; leakage current model; leakage mechanisms; normal operating voltage range; oxide thickness dependence; temperature dependence; trap-assisted tunneling; trench-type DRAM cells; Degradation; Diodes; Doping; Leakage current; Semiconductor process modeling; Temperature dependence; Temperature distribution; Tunneling; Ultra large scale integration; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.75708

Filename

75708