Title :
The impact of trench isolation on latch-up immunity in bulk nonepitaxial CMOS
Author :
Bhattacharya, S. ; Banerjee, S. ; Lee, J. ; Tasch, A. ; Chatterjee, A.
Author_Institution :
Microelectron. Res. Center, Texas Univ., Austin, TX, USA
Abstract :
Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates.<>
Keywords :
CMOS integrated circuits; VLSI; circuit layout; integrated circuit technology; semiconductor device models; ULSI; bulk nonepitaxial CMOS; conductivity-modulated well; deep trench isolation; design parameters; high packing densities; holding voltage; latch-up immunity; latch-up-free submicrometer CMOS; latchfree design; numerical simulations; parasitic bipolar current gain; submicron; theoretical understanding; trench dimensions; trench isolation impact; two-dimensional effects; two-dimensional spreading resistance; Anodes; CMOS technology; Cathodes; Conductivity; Large scale integration; PIN photodiodes; Substrates; Thyristors; Visualization; Voltage;
Journal_Title :
Electron Device Letters, IEEE
