• DocumentCode
    1496957
  • Title

    Massey-Omura type adder for elements of finite fields GF(2m ) in logarithmic representation

  • Author

    Drolet, G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada
  • Volume
    35
  • Issue
    5
  • fYear
    1999
  • fDate
    3/4/1999 12:00:00 AM
  • Firstpage
    368
  • Lastpage
    369
  • Abstract
    The multiplication, inversion, division and exponentiation of elements of GF(2m) are easily implemented with conventional arithmetic and logical units when the elements are in the logarithmic representation. An electronic architecture for the addition of two elements in the logarithmic representation is presented. The architecture of the adder is similar to that of the Massey-Omura multiplier for the normal basis representation. In particular, the same combinatorial circuit is used to successively compute every bit of the sum
  • Keywords
    Galois fields; adders; combinational circuits; digital arithmetic; logic design; Massey-Omura type adder; addition; combinatorial circuit; electronic architecture; finite fields; logarithmic representation; normal basis representation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990302
  • Filename
    757121
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1496957