A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology

A 50-Gb/s low-power analog equalizer has been realized in 65-nm CMOS technology. This equalizer adopts the proposed transformer feedback technique to achieve a peaking gain of 18 dB at 25 GHz and low-power dissipation. The whole equalizer without the output buffer consumes 10 mW from a 1-V supply. The chip occupies 0.35 times 0.27 mm². For a 50-Gb/s pseudorandom bit sequence of 2⁷ - 1 , the measured bit error rate is less than 10^-12, and the measured maximum root-mean-square and peak-to-peak jitters are 2.7 and 12.4 ps, respectively.