Technology mapping for simultaneous gate and interconnect optimisation

A technology mapping approach is presented which performs simultaneous gate and interconnect optimisation. For area optimisation, a cost function is proposed which takes into account both gate area and interconnect area to minimise the total chip area after layout. New techniques are proposed to estimate the interconnect cost and to calculate the gate cost more accurately. For delay optimisation, a new methodology is used to alleviate the effect of inaccurate delay models used at the mapping stage. A two-phase procedure is applied which combines technology mapping with postplacement logic resynthesis for minimising the interconnect delays. Show that this approach provides an reduction of 12% in the final chip area for area optimisation, and an average reduction of 17% in terms of postplacement delays for delay optimisation when compared with SIS 1.2