IR-Drop Management in FPGAs

Author

Kumar, Akhilesh ; Anis, Mohab

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada

Volume

29

Issue

6

fYear

2010

fDate

6/1/2010 12:00:00 AM

Firstpage

988

Lastpage

993

Abstract

This paper presents novel computer-aided design (CAD) techniques for mitigating IR-drops in field-programmable gate arrays (FPGAs). The proposed placement and routing relies on reducing the switching activities in local regions in the FPGA fabric to improve the profile of the supply voltage distribution. The proposed techniques reduce IR-drops and the variance of the supply voltage distribution across all the nodes in the power grid network. The proposed CAD techniques are efficient as they do not require solving the power grid model at every placement and routing iteration. A reduction of up to 53% in maximum IR-drop and up to 66% reduction in standard deviation of is obtained from the design techniques proposed in this paper with an average impact of 3% on circuit delay.

Keywords

circuit switching; electric potential; field programmable gate arrays; integrated circuit design; logic CAD; network routing; statistical analysis; voltage distribution; CAD; FPGA; IR-drop management; circuit delay; computer-aided design; field-programmable gate array; placement; power grid network; routing; standard deviation; supply voltage distribution; switching activity; voltage drop; Application software; Circuits; Delay; Design automation; Fabrics; Field programmable gate arrays; Power grids; Routing; Very large scale integration; Voltage; Computer-aided design (CAD); field-programmable gate array (FPGA); power grid; reliability; voltage drop;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2010.2043593

Filename

5467333