Title :
A two-level interleaving architecture for serial convolvers
Author :
Marino, Francescomaria
Author_Institution :
Dipt. di Elettrotecnica ed Eletron., Politecnico di Bari, Italy
fDate :
5/1/1999 12:00:00 AM
Abstract :
We present a bit-serial architecture for convolving/correlating long numerical sequences by long filter functions. Because of its two-level interleaving structure, the proposed device does not require “wait cycles” between consecutive input samples. As a result, it achieves the highest possible throughput. Cascadability, fault tolerance, feasibility in VLSI technology, and computing performances are discussed and analyzed
Keywords :
CMOS digital integrated circuits; VLSI; convolution; correlators; digital signal processing chips; fault tolerance; parallel architectures; pipeline arithmetic; sequences; CMOS; VLSI technology; bit-serial architecture; cascadability; computing performance; correlation; fault tolerance; input samples; long filter functions; long numerical sequences; pipelining; serial convolvers; serial/parallel multiplier; throughput; two-level interleaving architecture; Computer architecture; Convolvers; Diffraction; Fourier transforms; Interleaved codes; Performance analysis; Scattering; Shape measurement; Signal processing; Tomography;
Journal_Title :
Signal Processing, IEEE Transactions on
