Title :
Identification of Threshold Functions and Synthesis of Threshold Networks
Author :
Gowda, Tejaswi ; Vrudhula, Sarma ; Kulkarni, Niranjan ; Berezowski, Krzysztof
Author_Institution :
Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ, USA
fDate :
5/1/2011 12:00:00 AM
Abstract :
This paper presents a new and efficient heuristic procedure for determining whether or not a given Boolean function is a threshold function, when the Boolean function is given in the form of a decision diagram. The decision diagram based method is significantly different from earlier methods that are based on solving linear inequalities in Boolean variables that derived from truth tables. This method´s success depends on the ordering of the variables in the binary decision diagram (BDD). An alternative data structure, and one that is more compact than a BDD, called a max literal factor tree (MLFT) is introduced. An MLFT is a particular type of factoring tree and was found to be more efficient than a BDD for identifying threshold functions. The threshold identification procedure is applied to the MCNC benchmark circuits to synthesize threshold gate networks.
Keywords :
Boolean functions; benchmark testing; circuit testing; network synthesis; trees (electrical); Boolean function; MCNC benchmark circuits; binary decision diagram; heuristic procedure; max literal factor tree; threshold functions; threshold gate networks synthesis; threshold identification; threshold networks; Boolean functions; CMOS integrated circuits; Data structures; Dictionaries; Logic gates; Partitioning algorithms; Binary decision diagrams; Boolean algebra; Boolean function; logic design; logic optimization; logic synthesis; threshold function; threshold logic;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2010.2100232