Title :
Ultrafast shallow-buried-channel CCD´s with built-in drift fields
Author :
Lattes, A.L. ; Munroe, Scott C. ; Seaver, M.M.
Author_Institution :
MIT Lincoln Lab., Lexington, MA, USA
fDate :
3/1/1991 12:00:00 AM
Abstract :
The delay lines are operated with 5-V two-phase clocks, and a potential gradient is permanently built into the storage gates by a step implant in order to improve the charge transfer efficiency (CTE) at high clocking rates. The charge coupled devices (CCDs) with built-in drift fields were tested up to the 325-MHz limit of the existing clock drivers with no degradation in the CTE(>0.99996), while the equivalent CCDs with uniformly doped storage wells degrade rapidly above 240 MHz. These results are consistent with two-dimensional computer simulations.<>
Keywords :
charge-coupled device circuits; delay lines; integrated circuit technology; ion implantation; semiconductor device models; semiconductor doping; 325 MHz; 5 V; 99.996 percent; CTE; built-in drift fields; charge coupled devices; charge transfer efficiency; delay lines; high clocking rates; potential gradient; shallow buried channel CCDs; step doping; step implant; storage gates; two-dimensional computer simulations; two-phase clocks; ultrafast CCDs; Charge coupled devices; Circuit testing; Clocks; Degradation; Delay lines; Doping; Electrodes; Electrons; Implants; Linearity;
Journal_Title :
Electron Device Letters, IEEE
