DocumentCode
1498377
Title
Programmable spatial processing imager chip
Author
Gruev, V. ; Etienne-Cummings, R.
Author_Institution
Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
Volume
37
Issue
11
fYear
2001
fDate
5/24/2001 12:00:00 AM
Firstpage
688
Lastpage
690
Abstract
The authors present an architectural overview and results from an image processor chip for realising steerable spatial filtering at the focal plane. Convolutions of the image with multiple programmable kernels are realised with area-efficient, real-time circuits. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolutions are implemented with digitally programmable analogue processors. The chip performs 5.7 GOPS/mW while outputting four processed images in parallel
Keywords
CMOS analogue integrated circuits; CMOS image sensors; analogue processing circuits; convolution; focal planes; image processing equipment; spatial filters; convolutions; digitally programmable analogue processors; focal plane; image processor chip; multiple programmable kernels; processed images; programmable spatial processing; raw intensity image; real-time circuits; steerable spatial filtering;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010455
Filename
926443
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