Physically Based Modeling of Stress-Induced Variation in Nanoscale Transistor Performance

Uniaxial stress is widely used in advanced CMOS technologies to boost transistor performance. Conventional compact transistor models rely on empirical fitting of the average channel stress value to predict mobility and, hence, transistor performance. This approach can lead to significant errors for deeply scaled technologies. In this paper, stress profiles are modeled in analytical form, using a physically based approach. The stress model is validated by 3-D TCAD simulations. A nanometer-scale transistor intrinsic delay formula based on injection velocity theory is then applied. The predicted variation in transistor performance compares well with the measured silicon data for a 45-nm strained CMOS technology.