Title :
Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies
Author :
Moisiadis, Y. ; Bouras, I. ; Papadas, C. ; Schoellkopf, J.P.
Author_Institution :
Integrated Syst. Dev., Athens, Greece
fDate :
1/21/1999 12:00:00 AM
Abstract :
A low-voltage, high performance buffer suitable for implementation in standard CMOS technologies is proposed. The new buffer utilises the transient self back-bias (TSBB) technique to reduce electrically the threshold voltage of the output PMOS transistor, enhancing its performance. Simulations at 100 MHz and 0.9 V have shown that the TSBB buffer has a 35% speed advantage in the pull-up over the standard CMOS buffer. With only 5% increase in power dissipation
Keywords :
CMOS logic circuits; buffer circuits; leakage currents; low-power electronics; 0.9 V; 100 MHz; TSBB buffer; low-voltage high-performance applications; output PMOS transistor; power dissipation; pull-up; standard CMOS technologies; threshold voltage; transient self back-biased buffer;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990116
