Test Challenges for 3D Integrated Circuits

Author

Lee, Hsien-Hsin S. ; Chakrabarty, Krishnendu

Author_Institution

Georgia Inst. of Technol., Atlanta, GA, USA

Volume

26

Issue

5

fYear

2009

Firstpage

26

Lastpage

35

Abstract

One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area. Researchers are investigating various 3D IC manufacturing processes that are particularly relevant to testing and DFT. In terms of the process and the level of assembly that 3D ICs require, we can broadly classify the techniques as monolithic or as die stacking.

Keywords

design for testability; integrated circuit design; integrated circuit manufacture; integrated circuit testing; microassembling; 3D integrated circuit testing; DFT; IC assembly; IC manufacturing process; die stacking; monolithic stacking; Automatic testing; Circuit testing; Design automation; Design for testability; Electronic design automation and methodology; Integrated circuit testing; Manufacturing automation; Manufacturing processes; Stacking; Three-dimensional integrated circuits; 3D ICs; 3D integration; CMOS; DFT; defects; design and test; interconnect scaling;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/MDT.2009.125

Filename

5286146