Title :
3D DRAM Design and Application to 3D Multicore Systems
Author :
Sun, Hongbin ; Liu, Jibang ; Anigundi, Rakesh S. ; Zheng, Nanning ; Lu, Jian-Qiang ; Rose, Kenneth ; Zhang, Tong
Author_Institution :
Xi´´an Jiaotong Univ., Xi´´an, China
Abstract :
From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture.
Keywords :
DRAM chips; cache storage; multiprocessing systems; 3D DRAM design; 3D multicore system; cache stacking; memory bandwidth; Bandwidth; Bonding; Circuits; Computer architecture; Delay; Fabrication; Logic arrays; Multicore processing; Random access memory; Through-silicon vias; 3D integration; DRAM; design and test; memory hierarchy; multicore;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2009.105
