DocumentCode
1498846
Title
The fate of stacking
Author
Kung, David S.
Author_Institution
IBM T.J. Watson Research Center
Volume
26
Issue
5
fYear
2009
Firstpage
112
Lastpage
112
Abstract
The impending doom of CMOS scaling has semiconductor mavericks scrambling for alternative solutions to continue increasing the device density per chip. One serious candidate is 3D integration in which the planar manufacturing technology extends skyward into the third dimension, much like skyscrapers. Similarities between chip architecture and building architecture are plentiful, and the author draws some parallels between the two.
Keywords
Architecture; Buildings; CMOS technology; Floors; Licenses; Mass production; Semiconductor device manufacture; Stacking; Steel; Three-dimensional integrated circuits; 3D IC; CMOS scaling; design and test; stacking;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2009.127
Filename
5286158
Link To Document