The Impact of Dynamic Voltage and Frequency Scaling on Multicore DSP Algorithm Design [Exploratory DSP]

We connect to the two recent IEEE Signal Processing Magazine special issues on digital signal processing (DSP) on multicore processors (November 2009 and March 2010) and address an issue that was not addressed in the articles there, which we believe has important consequences for DSP algorithm design in the future. The basic observation that we start out with is that in DSP algorithm design, there is very often a tradeoff between the computational effort spent (in terms of the number of operations) and the quality/accuracy of the algorithm output. Herein we discuss the problems that emerge when optimizing algorithms for circuits that support the operation of several parallel cores that operate at different speeds. The understanding, formulation, and solution of these optimization problems require a cross-disciplinary approach that models the interplay between circuits, computer architecture, signal processing, and optimization. While allocation of computational and transmission resources for the purpose of saving energy is an established research topic in other fields (sensor network life time maximization being a notable example), there appears to be relatively little open literature on the type of problems that we discuss here. Taken together, we believe that the challenges we pose are important and that the signal processing algorithm design community is well positioned to tackle them.