Title :
Automated BIST for sequential logic synthesis
Author :
Stroud, Charles E.
Author_Institution :
AT&T Bell Labs., Naperville, IL, USA
Abstract :
An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. The approach has been incorporated in a system for behavioral model synthesis to implement BIST in VLSI devices based on standard cells and in circuit packs based on PLDs, automatically. Seven production VLSI devices have been implemented with this automated BIST approach. Area overhead was between 6% and 19% for a fault coverage of 90%+ with the BIST capability alone.<>
Keywords :
VLSI; automatic testing; logic CAD; logic testing; PLDs; VLSI devices; automated built-in self-test; behavioral model synthesis; device testing; sequential logic synthesis; system diagnostics; system memory elements; Automatic testing; Built-in self-test; Circuit testing; Flip-flops; Logic devices; Logic testing; Sequential analysis; System testing; Test pattern generators; Very large scale integration;
Journal_Title :
Design & Test of Computers, IEEE
