Title :
Optimal design of combinational logic circuits using genetic algorithm and Reed-Muller Universal Logic Modules
Author :
Vijayakumari, C.K. ; Mythili, P. ; James, Rekha K. ; Kumar, S. Akhil
Author_Institution :
Dept. of Electr. Eng., Rajiv Gandhi Inst. of Technol., Kottayam, India
Abstract :
Conventional design of digital circuits is a very complex task which requires much knowledge in domain-specific rules. But, combinational digital circuits can be evolved automatically using evolutionary techniques. This work proposes new approaches for the automated design of combinational digital circuits using Genetic Algorithm (GA) and Reed Muller Universal Logic module (RM ULM). Here 2-1 RM-ULM has been used as the only design unit for the automated design of combinational digital circuits. Certain modifications have been made on the existing Shannon´s decomposition technique for the design. Several circuits are synthesized with these modified methods and compared with the existing standard implementation technique using single control line Reed Muller Universal Logic Modules(RM ULM(1)). Manufacturing cost can be reduced by replicating the same element. With this method, the number of levels required as well as the number of modules needed is reduced considerably, thus reducing the cost, delay and power consumption.
Keywords :
combinational circuits; genetic algorithms; logic design; 2-1 RM-ULM; GA; Shannon decomposition technique; automated design; combinational digital circuits; digital circuits; domain-specific rules; evolutionary techniques; genetic algorithm; optimal combinational logic circuits design; power consumption; single control line Reed Muller universal logic modules; Biological cells; Convergence; Digital circuits; Embedded systems; Genetic algorithms; Ice; Standards; Evolutionary techniques; Genetic Algorithm (GA); RM-ULM; Shannon´s decomposition method;
Conference_Titel :
Embedded Systems (ICES), 2014 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-5025-6
DOI :
10.1109/EmbeddedSys.2014.6953039