Title :
PROUD: a sea-of-gates placement algorithm
Author :
Tsay, Ren-Song ; Kuh, Ernest S. ; Hsu, Chi-Ping
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
An efficient method is proposed for placing modules in large and highly complex sea-of-gates chips that include preplaced I/O pads and macrocells. PROUD repeatedly solves sparse linear equations. A resistive network analogy of the placement problem and convexity of the objective function are key concepts in this algorithm. The algorithm was tested on nine real circuits. For a triple-metal-layer, 100000-gate sea-of-gate design with 26000 instances, the constructive phase took 50 minutes on a VAX 8650 and yielded excellent results for total wire length. Extensions of the method are considered.<>
Keywords :
circuit layout CAD; PROUD; VAX 8650; convexity; macrocells; modules; resistive network analogy; sea-of-gates placement algorithm; sparse linear equations; Aircraft; Application specific integrated circuits; Eigenvalues and eigenfunctions; Equations; Gaussian processes; Joining processes; Simulated annealing; Sparse matrices; Symmetric matrices; Wire;
Journal_Title :
Design & Test of Computers, IEEE
