Hardware implementation of quasigroup based encryption

This paper presents a Hardware implementation of Quasigroup based encryption with pipelining to reduce the encryption time. Unlike number system based approaches, it requires only simple table lookup operations thereby enabling efficient hardware implementation. A hardware model of the encryption is proposed and synthesized to an FPGA library. Quasigroup based encryption is less affected by brute force attacks compared to the conventional methods because the number of quasigroups increases as the order increases in an astronomical fashion. The architecture of the proposed design is synthesized and implemented in Altera Cyclone II FPGA kit. The robustness of the scheme is further improved by permutation in of the quasigroup in each step. The proposed hardware utilizes less memory as it does not need to store all the permuted quasigroups. The robustness of the implemented design is evaluated using the NIST-STS Test Suite.