DocumentCode
1499366
Title
Design-Aware Mask Inspection
Author
Kagalwalla, Abde Ali ; Gupta, Puneet ; Progler, Christopher J. ; McDonald, Steve
Author_Institution
Dept. of Electr. Eng., Univ. of California at Los Angeles, Los Angeles, CA, USA
Volume
31
Issue
5
fYear
2012
fDate
5/1/2012 12:00:00 AM
Firstpage
690
Lastpage
702
Abstract
Mask inspection has become a major bottleneck in the manufacturing flow taking up as much as 40% of the total mask manufacturing time. In this paper, we explore techniques to improve the reticle inspection flow by increasing its design awareness. We develop an algorithm to locate nonfunctional features in a postoptical proximity correction layout without using any design information. Using this, and the timing information of the design (if available), the smallest defect size that could cause the design to fail is assigned to each reticle feature. The criticality of various reticle features is then used to partition the reticle such that each partition is inspected at a different pixel size and sensitivity so that the false and nuisance defect count is reduced without missing any critical defect. We also develop an analytical model to estimate the false and nuisance defect count. Using those models, our simulation results show that this design-aware mask inspection can reduce the false and nuisance defect count for a critical polysilicon layer from 80 defects down to 49 defects, leading to substantial reduction in defect review load. We also develop a model to estimate first pass yield (FPY) and show that our method can improve the FPY for a polysilicon layer from 11% to 30%. Apart from the polysilicon layer, the potential benefit of this approach is analyzed for active, contact and all the metal/via layers.
Keywords
crystal defects; design for manufacture; elemental semiconductors; inspection; proximity effect (lithography); reticles; semiconductor industry; sensitivity; silicon; critical polysilicon layer; defect size; design awareness; design-aware mask inspection; false count reduction; first pass yield estimation; mask manufacturing time; nonfunctional features; nuisance defect count reduction; pixel size; postoptical proximity correction layout; reticle features; reticle inspection flow improvement technique; sensitivity; timing information; Delay; Inspection; Layout; Metals; Sensitivity; Shape; Computer-aided design (CAD); design for manufacturability (DFM); mask inspection; mask manufacturing; reticle; semiconductor manufacturing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2011.2181909
Filename
6186861
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