Inductance calculation and optimal pin assignment for the design of pin-grid-array and chip carrier packages

Author

Shrivastava, Udbhava A. ; Bui, B. Lan

Author_Institution

Motorola Inc., Phoenix, AZ, USA

Volume

13

Issue

1

fYear

1990

fDate

3/1/1990 12:00:00 AM

Firstpage

147

Lastpage

153

Abstract

A methodology for the calculation of self- and mutual inductance of various electrical paths in a pin-grid array (PGA) or a chip carrier package is described. An N×N inductance matrix is generated for a package, where N is determined by the number of pins, power, and ground planes. Theory, algorithms, and software have been developed to compute the effective inductance of multiply coupled inductors. The software estimates the number of pins for a specified value of inductance and computes the effective inductance for sets of pins chosen for various functions. In this manner, several groups of pin assignments can be evaluated to obtain the smallest effective inductance. The design software computes a 132×132 inductance matrix in about 45 min on an HP 9040 computer. Illustrative examples of pin assignments for power and ground pins in single- and multilayer packages are provided. Good agreement between calculation and experiment was found for packages with pin counts varying from 68 to 289. Design guidelines for pin assignments and placement of power distribution planes in a single- or multilayer package are given for low-inductance package design

Keywords

CAD; VLSI; digital integrated circuits; electronic engineering computing; inductance; optimisation; packaging; HP 9040 computer; N×N inductance matrix; chip carrier packages; ground pins; inductance calculation; inductance of multiply coupled inductors; low-inductance package design; multilayer packages; mutual inductance; optimal pin assignment; pin assignments; pin counts 68 to 289; pin-grid-array; placement of power distribution planes; self inductance; single layer packages; Electronics packaging; Guidelines; Inductance; Inductors; Nonhomogeneous media; Pins; Power distribution; Power generation; Software algorithms; Software design;

fLanguage

English

Journal_Title

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Publisher

ieee

ISSN

0148-6411

Type

jour

DOI

10.1109/33.52863

Filename

52863