SEGRA: a very fast general area router for multichip modules

We present a very fast area router for multichip module (MCM) design. Given a set of nets and a routing area, the router repeatedly selects two layers from top to bottom and routes as many nets as possible until all the nets are routed. The router uses a line sweep technique and a simple net selection algorithm. By employing efficient data structures and a novel priority scheme, the routing can be completed in time almost proportional to the size of the routing area. When applied to the benchmark circuits, the proposed router generated comparable routing results 23 times faster on the average than the previously reported fastest and effective router. When compared with the previously reported best routing result achiever, our router produced slightly worse results but ran 102 times faster on the average. Its effectiveness and ultra fast computation time make this router ideally suited for the next generation of large scale MCM designs