Title :
Design of low power split path Data Driven Dynamic ripple carry adders
Author :
Arun ; Kumar, Manoj
Author_Institution :
Dept. of Electron. & Commun. Eng., Guru Jambheshwar Univ. of Sci. & Technol., Hisar, India
Abstract :
Addition is the fundamental operation used in computer arithmetic circuits and CMOS adder is the basic component of these systems. This paper presents the designs of new 4-bit and 8-bit split-path Data Driven Dynamic logic (sp-D3L) ripple carry adder (RCA) circuit. Power consumption of proposed 4-bit RCA´s varies from 0.69nW to 2.75nW with variation in supply voltage from 1.8V to 3.3V. Maximum output delay shows variation from 55.42ps to 245.98ps. Power consumption of proposed 8-bit RCA´s varies from 1.37nW to 5.52nW with variation in supply voltage from 1.8V to 3.3V. Maximum output delay shows variation from 54.96ps to 246.25ps. Simulations have been performed using SPICE based on TSMC 0.18μm CMOS technology. Power consumption and delay of proposed RCA adder circuit have been compared with earlier reported circuits and proposed circuit shows better performance.
Keywords :
CMOS logic circuits; SPICE; adders; carry logic; logic design; low-power electronics; power consumption; CMOS adder; RCA adder circuit; SPICE; TSMC CMOS technology; addition; computer arithmetic circuits; designs; low power split path data driven dynamic ripple carry adders; maximum output delay; power consumption; ripple carry adder circuit; size 0.18 mum; sp-D3L; split-path data driven dynamic logic; word length 4 bit; word length 8 bit; Adders; CMOS integrated circuits; Delays; Power demand; Propagation delay; Transistors; Very large scale integration; Arithmetic circuits; CMOS; RCA; full adder; split-path D3L;
Conference_Titel :
Computing for Sustainable Global Development (INDIACom), 2014 International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-93-80544-10-6
DOI :
10.1109/IndiaCom.2014.6828008
