DocumentCode :
1500087
Title :
Measurement and Simulation of Stacked Die Thermal Resistances
Author :
Joiner, Bennett ; De Oca, Jose A Montes ; Neelakantan, Sriram
Author_Institution :
Dept. of Global Package Eng., Freescale Semicond., Inc., Austin, TX, USA
Volume :
32
Issue :
4
fYear :
2009
Firstpage :
709
Lastpage :
715
Abstract :
Packages with multiple dies provide additional challenges when documenting their thermal performance. One style of multiple dies packages stacks the die on top of each other with a die attach adhesive. This paper explores the thermal performance of such packages in a wire bond plastic ball grid array package with three different die configurations. The thermal performance of the package was determined using the JEDEC JESD51 specifications. Since there were three different effective die sizes, the data allowed a better validation of the finite element thermal simulation techniques than can be obtained with only a single die size. Die size is usually the most important predictor of plastic ball grid array thermal performance. In this case, packages built with the same materials and substrate had a Theta-JA (2s2p board, natural convection) that differed by 100% as a result of a change in effective die size. With a validated simulation method, additional power distributions were simulated and compared to results obtained by superposition techniques.
Keywords :
ball grid arrays; lead bonding; plastic packaging; thermal resistance measurement; JEDEC JESD51 specifications; die attach adhesive; power distributions; simulation method; stacked die thermal resistance measurement; superposition techniques; wire bond plastic ball grid array package; Integrated circuit; PBGA; Theta-JA; multichip; package; stacked; superposition; thermal;
fLanguage :
English
Journal_Title :
Components and Packaging Technologies, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3331
Type :
jour
DOI :
10.1109/TCAPT.2009.2028813
Filename :
5286847
Link To Document :
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