Title :
High-speed DRAM architecture development
Author :
Ikeda, Hiroaki ; Inukai, Hidemori
Author_Institution :
NEC Corp., Sagamihara, Japan
fDate :
5/1/1999 12:00:00 AM
Abstract :
This paper is an overview of the high-speed DRAM architecture developments. We discuss developments on density growth, interface technology, memory-core architecture, and DRAM+ASIC technology. We can find the developments of density as 2× growth instead of 4× by each generation. Interface technologies will have a tendency to use the terminated bus structure for higher data rate. Memory-core architecture developments are the trials for actual bandwidth improvements. DRAM+ASIC technologies seem to require universal interface solutions. We tried to show that no single solution is able to cover the wide diversity of future system requirements
Keywords :
DRAM chips; application specific integrated circuits; high-speed integrated circuits; memory architecture; DRAM architecture development; DRAM+ASIC technology; SDRAM; bandwidth improvements; density growth; dynamic RAM; high-speed DRAM; interface technology; memory-core architecture; synchronous DRAM; terminated bus structure; Application specific integrated circuits; Bandwidth; Clocks; Delay; Diversity reception; Mass production; Memory architecture; Random access memory; Research and development; SDRAM;
Journal_Title :
Solid-State Circuits, IEEE Journal of
