DocumentCode :
1501241
Title :
Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices
Author :
Ha, Daewon ; Cho, Changhyun ; Shin, Dongwon ; Koh, Gwan-Hyeob ; Chung, Tae-Young ; Kim, Kinam
Author_Institution :
Technol. Dev., Samsung Electron. Co., Kyungki, South Korea
Volume :
46
Issue :
5
fYear :
1999
fDate :
5/1/1999 12:00:00 AM
Firstpage :
940
Lastpage :
946
Abstract :
As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction
Keywords :
DRAM chips; VLSI; densification; ion implantation; isolation technology; leakage currents; nitridation; STI dislocations; anomalous junction leakage current; deep submicron devices; densification temperature; depletion region; dynamic random access memory devices; giga-bit regime; implantation condition; mechanical stress; memory cell data retention time; process-induced defects; rapid thermal nitridation; shallow trench isolation; source/drain implantation; standby current; trench filled high-density plasma oxide; Annealing; DRAM chips; Fabrication; Isolation technology; Leakage current; Oxidation; Plasma temperature; Random access memory; Size control; Thermal stresses;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.760401
Filename :
760401
Link To Document :
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