Methodology for Design Optimization of SOI FinFET Grounded-Gate NMOS Devices

A new design methodology for FinFET devices is presented, which takes into account all complex dependences on both layout and process parameters of the electrostatic discharge (ESD) electrical device parameters of NMOS FinFET devices operating in parasitic bipolar mode. This methodology allows optimization toward a given ESD target (area consumption, leakage current, voltage drop, parasitic capacitance, etc.) while fulfilling several imposed design constraints. Fundamental insights are obtained regarding the different design and device tradeoffs.