Piecewise-linear timing delay modeling for digital CMOS circuits

A simple and accurate timing delay characterization algorithm for digital complementary metal-oxide-semiconductor (CMOS) circuits is presented. To reflect various nonlinear effects in metal-oxide-semiconductor circuits, the author uses reliable circuit simulations and measurements to generate various timing data for the most typical subcircuit structures with various driving and loading conditions. The huge data set is curve-fitted into simple piecewise-linear functions, which are stored in a timing library. Great efficiency and reliable accuracy are achieved on an experimental simulator based on the precharacterized timing library