I/O standard based power optimized processor register design on ultra scale FPGA

In design and implementation of energy efficient register, we are using different I/O standard in 28nm Artix-7 FPGA, Verilog, Xilinx ISE 14.6 as simulator and XPower 14.6 as energy estimator and analyzer tool. This register is a building block of energy efficient processor based on LVCMOS (Low Voltage Complementary Metal Oxide I/O, HSTL(High Speed Transistor Logic), HSUL standard in FPGA. This design is implemented on 28nm 7 Series Kintex-7 (7k70tfbg676-3) FPGA. When register operates in range of 1GHz-1THz, the reduction in I/O energy frittering of register for LVCMOS15 is 25.37%, 57.80%, 75.18% lesser of LVCMOS18, LVCMOS25 and LVCMOS33 respectively. When register operates at 1 GHz, the reduction in I/O energy dissipation of HSTL_II is 25.48%, 57.78%, 75.20% lesser of HSTL_I, HSTL_I_18 and HSTL_II_18 respectively. LVCMOS15 is the most energy efficient IO standard whereas LVCMOS33 is the worst energy fritter. HSTL_II is the least energy fritter I/O standards whereas HSTL_I_18 is the highest energy fritter among all available 4 different HSTL I/O standard.