Impact of finite impulse response digital-toanalogue converter delay on the stability of continuous-time sigma-delta modulators with pulse-with modulation in the feedback path

A finite impulse response (FIR) digital-to-analogue converter (DAC) in the feedback path has been shown to reduce the sensitivity to clock jitter of continuous-time sigma-delta modulators (SDMs). A method to analyse the impact of the additional loop delay introduced by the FIR-DAC on the modulator stability is proposed in this paper. This method is applied to the pulse width modulated (PWM) SDM. As in the PWM-SDM the pulse-width modulator is sampled at a frequency higher than the quantiser, a discrete time model is first obtained which operates with only one clock. The stability analysis is based on a linear model with a new criterion which takes into account the quantiser overloading. The theoretical results are in accordance with the results obtained by simulation. Here, it is shown that PWM-SDMs with an order greater than 2 can be designed maintaining the low sensitivity of multiple feedback architectures to a delay in the outer loop.