DocumentCode :
1502724
Title :
A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver
Author :
Liu, Lechang ; Sakurai, Takayasu ; Takamiya, Makoto
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan
Volume :
46
Issue :
6
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
1349
Lastpage :
1359
Abstract :
A 1.2 V 100 Mb/s 2.93 mW discrete-time charge-domain impulse radio ultra-wideband (IR-UWB) receiver is developed in 65 nm CMOS. In the charge-domain, the template of the correlator is represented by capacitance and the correlation is implemented by charge addition instead of voltage multiplication and voltage integration. Power consumption of the charge-domain receiver is minimized by a novel auto- and cross-correlation based synchronization scheme. To reduce the power consumption and the chip area of the PLL clock generator for the receiver, a dual charge-pump PLL is proposed to scale up the capacitance of the loop filter without extra charge-pump current. The developed UWB receiver with the area- and power-efficient PLL achieves the energy consumption of 29.3 pJ/bit with the 62.5-ps timing step for data synchronization.
Keywords :
CMOS integrated circuits; low-power electronics; phase locked loops; CMOS; IR-UWB receiver; PLL clock generator; area-efficient PLL; auto-correlation based synchronization scheme; charge-domain auto-correlation based data synchronization scheme; charge-domain receiver; cross-correlation based data synchronization scheme; cross-correlation based synchronization scheme; discrete-time charge-domain impulse radio ultra-wideband; dual charge-pump PLL; energy consumption; impulse radio UWB receiver; power consumption; power-efficient PLL; voltage integration; voltage multiplication; Clocks; Correlation; Correlators; Phase locked loops; Receivers; Synchronization; DLL; PLL; UWB; Ultra-wideband; auto-correlation; capacitance multiplier; charge-domain; cross-correlation; delay-locked loop; phase-locked loop;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2011.2128210
Filename :
5755128
Link To Document :
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