Simulation of high-speed interconnects

Author

Achar, Ramachandra ; Nakhla, Michel S.

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

Volume

89

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

693

Lastpage

728

Abstract

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail

Keywords

VLSI; circuit simulation; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; reduced order systems; transmission line theory; VLSI design; circuit simulation; high-speed interconnect; model reduction algorithm; transmission line macromodel; Application software; Computational modeling; Delay effects; Design automation; Distortion; Frequency; Large scale integration; Packaging; Reflection; Very large scale integration;

fLanguage

English

Journal_Title

Proceedings of the IEEE

Publisher

ieee

ISSN

0018-9219

Type

jour

DOI

10.1109/5.929650

Filename

929650