• DocumentCode
    1503421
  • Title

    Differential pass-transistor clocked flipflop

  • Author

    Hwang, In-Chul ; Kang, Sung-Mo

  • Author_Institution
    Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
  • Volume
    37
  • Issue
    12
  • fYear
    2001
  • fDate
    6/7/2001 12:00:00 AM
  • Firstpage
    732
  • Lastpage
    734
  • Abstract
    A new differential pass-transistor clocked (DPTC) flipflop for low power application is presented. This design prevents speed degradation and redundant power consumption by cutting the low-impedance path of the struggling slave latch in the conventional pass-transistor clocked flipflop. Simulation results show that it reduces the power-delay product by 30% and the delay mismatch between two differential outputs to <2%
  • Keywords
    CMOS logic circuits; flip-flops; low-power electronics; timing; 0.35 micron; delay mismatch reduction; differential pass-transistor clocked flipflop; low power application; power-delay product reduction;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010530
  • Filename
    929661
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1503421