• DocumentCode
    1503428
  • Title

    Low-voltage fourth-order CMOS sigma-delta modulator implementation

  • Author

    Lampinen, H. ; Vainio, O.

  • Author_Institution
    Lab. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
  • Volume
    37
  • Issue
    12
  • fYear
    2001
  • fDate
    6/7/2001 12:00:00 AM
  • Firstpage
    734
  • Lastpage
    735
  • Abstract
    A low-voltage, high-speed, fourth-order sigma-delta modulator implementation is presented. The low-voltage and high-speed operation are obtained by using a novel combination of architectural features, proper circuit structure selections, specific clocking strategies, and efficient circuit optimisation algorithms. Measurement results from fabricated CMOS chip prototypes show a good match with simulations
  • Keywords
    CMOS integrated circuits; circuit optimisation; high-speed integrated circuits; low-power electronics; mixed analogue-digital integrated circuits; modulators; sigma-delta modulation; timing; A/D convertors; ADC; ASIC; CMOS sigma-delta modulator implementation; LV fourth-order sigma-delta modulator; circuit optimisation algorithms; clocking strategies; high-speed operation; low-voltage operation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010502
  • Filename
    929662
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1503428