Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction

Author

Sotiriadis, Paul P. ; Galanopoulos, Kostas

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece

Volume

59

Issue

5

fYear

2012

fDate

5/1/2012 12:00:00 AM

Firstpage

958

Lastpage

968

Abstract

Direct all-digital frequency synthesizers are favored by modern nanoscale CMOS technologies but suffer from strong frequency spurs and timing irregularities. To counter these drawbacks various jitter-correction and spurs-suppression techniques have been proposed. This paper presents a comprehensive literature review and a comparative study of such techniques, applied to popular direct all-digital frequency synthesis cores, identifying their strengths and weaknesses.

Keywords

CMOS integrated circuits; frequency synthesizers; jitter; deterministic jitter correction; direct all-digital frequency synthesis; direct all-digital frequency synthesizers; nanoscale CMOS technologies; spurs suppression; strong frequency spurs; timing irregularities; Adders; Clocks; Delay; Frequency conversion; Frequency synthesizers; Jitter; Registers; Clock generation; digital-to-frequency converter; direct digital period synthesis; direct digital synthesis; flying adder; frequency spurs; frequency synthesis; jitter; phase accumulator;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2012.2191875

Filename

6190729