Carrier and symbol synchronization in digital receivers using feedback compensation loop and early late gate on FPGA

This paper deals with the complete design of a digital communication receiver on FPGA. Carrier and timing synchronization problems are covered in implementation. Carrier recovery is done using a feedback compensation loop and timing recovery is done using an early late gate. Xilinx ISE is used for simulation and synthesis and the virtex-6 FPGA board is chosen as the hardware platform. Results obtained are highly accurate with very low bit error rate under noisy environment consisting of additive white Gaussian noise (AWGN) channel and variable delays. FPGA results are also presented.