Title :
High-drive CMOS buffer for large capacitive loads
Author :
Nosratinia, Aria ; Ahmadi, Mahdi ; Jullien, G.A. ; Shridhar, M.
Author_Institution :
Dept. of Electr. Eng., Windsor Univ., Ont., Canada
fDate :
6/6/1991 12:00:00 AM
Abstract :
A new CMOS buffer circuit for high capacitive loads is presented. The objective of the design is a high-power, area-efficient buffer to be used in very large scale analogue applications. The buffer can deliver a slew rate of 1.2 V/ mu s to capacitive loads in excess of 5000 pF. It has a total harmonic distortion of less than 3% at 20 kHz. At stand by, it consumes only 125 mu A (0.625 mW). The buffer occupies 100 mils2 of die area in a 3 mu m technology.
Keywords :
CMOS integrated circuits; buffer circuits; driver circuits; linear integrated circuits; operational amplifiers; 0.625 mW; 125 muA; 3 micron; 5000 pF; CMOS buffer circuit; area-efficient buffer; high drive buffer; high-power; large capacitive loads; very large scale analogue applications;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19910649
