DocumentCode
1504243
Title
PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design
Author
Wu, Tai-Hsuan ; Davoodi, Azadeh
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA
Volume
28
Issue
11
fYear
2009
Firstpage
1666
Lastpage
1678
Abstract
We propose Parallel and Randomized cell Sizing (PaRS), a parallel and randomized algorithm and tool to solve the discrete gate sizing (cell sizing) problem on a grid. PaRS is formulated based on an optimization framework known as nested partitions which we adopt for the first time in the computer-aided design area. PaRS uses parallelism from a novel perspective to better identify the optimization direction. It achieves near-optimal solutions (under 1%) for minimizing the total power subject to meeting a delay constraint. The embarrassingly parallel nature of PaRS makes it highly scalable. We show small algorithm runtimes, in at most minutes for large benchmarks featuring over 47 000 cells. We make comparison with the optimal solution which we are able to generate using customized and parallel branch-and-bound implementation on a grid. Consequently, we are able to generate the optimal solution within hours. While the optimal algorithm uses up to 200 central processing units (CPUs) on our grid, PaRS achieves significant speedups and near-optimal solutions using only 20 CPUs. We also study the impact of varying number of CPUs in PaRS. Finally, we discuss a grid-based implementation using the ldquomaster-workerrdquo framework.
Keywords
circuit CAD; circuit optimisation; integrated circuit design; parallel algorithms; PaRS; central processing units; computer-aided design area; discrete gate sizing problem; library-based design; master-worker framework; near-optimal grid-based cell sizing; near-optimal solutions; nested partitions; optimization framework; parallel and randomized cell sizing; parallel branch-and-bound implementation; randomized algorithm; Algorithm design and analysis; Delay estimation; Design automation; Design optimization; Libraries; Mesh generation; Parallel processing; Partitioning algorithms; Runtime; Sampling methods; Cell sizing; cloud computing; combinatorial optimization; nested partitions; parallel optimization;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2009.2028682
Filename
5290357
Link To Document